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YSS950
DAP1
Digital Audio Processor Outline
The YSS950 (DAP1) is a DSP (Digital Signal Processor) for sound field processing, which features a high-speed/ high-precision 32-bit floating point DSP.
Features
32-bit floating point DSP achieves high-speed/high-precision operations * Operation frequency: Approximately 166 MHz * Data bus width: 32 bits (24-bit mantissa, 8-bit exponent) * Multiplier/adder: 32 bits x 32 bits + 55 bits 55 bits (47-bit mantissa, 8-bit exponent) 48 KB (12 Kword) preset command code firmware area 24 KB (6 Kword) download command code firmware area (maximum) 104 KB (26 Kword) data RAM area (maximum) High-speed command code/coefficient data firmware download (burst transfer) Download coefficients data firmware without any interruption of sound (runtime transfer) Firmware's placement order can be changed Firmware's number of execution channels can be changed (up to 16 channels) Multiple firmware calls are enabled Audio I/O * 32 bits x 16 channels, TDM * Fixed point decimal format and floating point decimal format (IEEE Standard 754, two's complement) * Sampling frequency range is 32 to 192 kHz * Audio clock division/switch * Input/output muting * Input/output channel switching External memory not required General I/O ports (4) On-chip PLL Power supply voltage: 1.2 V (core), 3.3 V (pin) Low power consumption: Approximately 130mW (typical value) Si-gate CMOS process Lead-free 64-pin SQFP package (YSS950-SZ)
Applications
Home theater systems Car audio
YSS950 CATALOG CATALOG No.: LSI-4SS950A22 2006.10
YSS950
Block Diagram
SDIMCK SDIBCK SDIWCK SDI0 SDI1 SDI2 SDI3 SDI4 SDI5 SDI6 SDI7 Serial Data Input 32bit Floating-Point DSP Serial Data Output
SDOMCK SDOBCK SDOWCK SDO0 SDO1 SDO2 SDO3 SDO4 SDO5 SDO6 SDO7
/RST XI PLL XO TEST4-0 /CS SCK SI Instruction/Data RAM 28K x 32 Instruction/Data ROM 24K x 32
/INT /MUTE Registers GPIO3-0
Serial Peripheral Interface SO
System Configuration Example
Microprocessor
DIR or ADC or DSP
YSS950
DIT or DAC or DSP
2
YSS950
Application Firmware
The application firmware of YSS950(DAP1) provides a variety of functions that can be used in home theater systems, car audio systems, and many other applications. This application firmware can be combined to implement signal flow for up to 16 channels.
Firmware Name Abbr. Function
Bass manager Channel divider Delay Down sampler Dynamic range controller Format converter Generator High frequency regenerator Headphone surround IIR1x2 IIR2x2 IIR2x3 IIR2x8 Mixer Sound field Virtual surround Volume controller Acoustic Field Analyzer Dolby Pro Logic II Dolby Pro Logic IIx
BM CD DLY DS DRC FMT GEN HR HS I12 I22 I23 I28 MIX SF VS VOL AFA PLII PLIIx
Distributes the optimum low-range signal for the playback environment. Divides bandwidth for multi-way. Adds delay to individual channels. Down samples to 1/2. Controls dynamic range. Converts signal format. Generates a noise signal or impulse signal. Complements high frequency components. Reproduces 5.1 channel surround on headphones. A cascade of two 1st-order IIR filters. A cascade of two 2nd-order IIR filters. A cascade of three 2nd-order IIR filters. A cascade of eight 2nd-order IIR filters. Signal gain can be applied freely. Sounds reverb richly. Reproduces 5.1 channel surround on only the front speaker. Overall and channel-specific volume adjustments. Measurement of audio characteristics. for Automatic Acoustic Field Calibration system. Dolby Pro Logic II decoder. Dolby Pro Logic IIx decoder.
Up to 24 application firmware modules can operate at the same time. The information shown above is subject to revision. Check with Yamaha or an authorized sales agency for the latest information before using this product..
3
YSS950
Development/Evaluation Kits
Development/Evaluation Kits are prepared for the evaluation and the firmware development of YSS950.
Development/ Evaluation Kit Name DMB-DAP1 Category Evaluation Board Program Tools Description Evaluation board. Curcuit_Diagram of evaluation board. EVBDSP EVBDSP is a control program that controls an evaluation board from a personal computer , via a USB connection. This program can be used to evaluate the YSS950's functions. DAP1Mapper DAP1Mapper is a tool that determines memory map of the YSS950 (DAP1) firmware. Fltcnvc Fltcnvc is a command line tool that converts tool between two's complement floating point format and real number format. iirdgn iirdgn is a command line tool that calculates the coefficients of typical IIR filters. DRCDesigner DRCDesigner is an Excel file that is used to create sample files for the dynamic range controller firmware. DAP1AFC The DAP1AFC is a tool that works with firmware (AFA1) on the DAP1 evaluation board (hereafter, "evaluation board") to measure audio characteristics at the listening point, and automatically makes calibration to set the specified characteristics. BM CD DLY DS DRC FMT GEN HR HS I12 I22 I23 I28 MIX SF VS VOL AFA PLII PLII Automatic Acoustic Field Calibration Coefficient Calculation Program. AFA The same as firmware AFA included in DAP1AFC.
Application Firmware
AS-DAP1-PLII AS-DAP1-PLIIx AS-DAP1-AFA
Application Firmware Application Firmware Automatic Acoustic Field Calibration system
[Caution]
The information shown above is subject to revision. information before using this product. Check with Yamaha or an authorized sales agency for the latest
[Caution] "Dolby", "Dolby Pro Logic II", and "Dolby Pro Logic IIx" are trademarks of Dolby Laboratories. "DTS", "DTS-ES", "DTS-96/24", and "DTS Neo:6" are trademarks of Digital Theater Systems, Inc.
1
AFA: Acoustic Field Analyzer
4
YSS950
Comparison of Yamaha audio DSP
Chip Name Function Dolby digital decoding Dolby Digital EX decoding AAC decoding PCM input playback Dolby Pro Logic II decoding Dolby Pro Logic IIx decoding DTS decoding DTS 96/24 decoding DTS-ES decoding DTS Neo:6 decoding Tone control Bass management Volume adjustment Noise generation Impulse generation Firmware Dynamic range controller Harmonics regenerator Nch surround Sound field Virtual surround Headphone surround Parametric equalizer Graphic equalizer Channel divider Automatic acoustic calibration Down mixing Mixer Down sampling Modification of firmware placement Multiple firmware calls User programmability Precision of calculations Microcontroller interface Firmware download Digital audio interface Audio data channel switching control Bypass User mute External memory interface Hardware Input delay (lip sync) Output delay Stream detection Auto mute Status port General-purpose I/O ports Internal operation clock generator Power-up/power-down Operation frequency Power supply voltage Power consumption (Typ.) Package Lead-free 130 mW SQFP64 Y Y 24 bits (fixed) or 32 bits (floating) x 16 channels, TDM (4 channels or 8 channels) is enabled Y (input and output) Y Y (input and output) N Y Y N Y Auto mute, interrupt 4 Y Y 165.888 MHz DAP1 YSS950 N N N Y (up to 16 channels Y Y N N N N Y Y Y Y Y Y Y Y (Mixer) Y Y Y Y (8ch x 8Band x X) Y (PEQ implementation) Y Y Y (Mixer) Y Y (16 channels) Y Y Y (design with module) Y Y Y Y YSS944 ADAMB YSS943 Y Y Y Y (up to 8 channels Y Y Y Y N N Y Y Y Y Y Y N Y Y Y Y Y (8ch x 5Band) Y (PEQ implementation) Y Y Y N Y (2 channels) N N N N N N N YSS940 EVE YSS920B N N N Y (up to 16 channels) N N N N N N Y Y Y Y Y Y N Y(Channel Distributor) Y Y N Y (5ch x 3Band) Y(2ch x 10band) Y N Y Y N N N Y(design with assembler) Internal data bus:32-bit floating point (28-bit mantissa, 4-bit exponent), Coefficient : 16-bit fixed point Y 24 bits (fixed) or 32 bits (floating) x 16 channels N Y (realize by firmware) Y (output) DRAM or SRAM (4Mbit) Y Y N N Zero detection, etc 20 Y N 50MHz 2.5V (core), 3.3V (pin) 165mW SQFP100 Y
Internal data bus:32-bit floating point (24-bit mantissa, 8-bit exponent), Coefficient : 32-bit floating point Four-wire serial interface Y 24 bits (fixed) x8 channels Y (output) Y Y (output) SRAM (4Mbit) Y Y Y Y Zero detection, auto mute, interrupt 8 Y Y 178.176MHz 1.2V (core), 3.3V (pin) 211mW (Dolby Digital decoding) LQFP144 Y
[Caution] "Dolby", "Dolby Pro Logic II", and "Dolby Pro Logic IIx" are trademarks of Dolby Laboratories. "DTS", "DTS-ES", "DTS-96/24", and "DTS Neo:6" are trademarks of Digital Theater Systems, Inc.
5
YSS950
Pin Configuration
SDOWCK 34
SDOMCK
SDOBCK
VDD12
VDD12
VDD33
SDO0
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
33
VSS
VSS /CS SCK SI SO /INT VDD33 VDD12 VDD12 /MUTE /RST TEST4 VSS PAVDD PAVSS PAVDD
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS SDIWCK SDIBCK SDIMCK SDI7 SDI6 VDD33 VDD12 VDD12 SDI5 SDI4 SDI3 SDI2 SDI1 SDI0 VSS
1
2
3
4
5
6
7
8
VSS
9
PAVSS
PDVSS
TEST0
TEST1
TEST2
PDVDD
< 64-pin SQFP top view >
6
VDD12
TEST3
GPIO0
GPIO1
GPIO2
GPIO3
VSS
XO
XI
YSS950
Pin Function List
Type Serial peripheral interface (SPI) Pin No. 50 51 52 53 29 30 31 18 19 20 21 22 23 27 28 36 35 34 47 46 45 44 43 42 38 37 Status 54 58 General-purpose 10 I/O ports 11 12 13 System 59 7 Pin Name /CS SCK SI SO SDIMCK SDIBCK SDIWCK SDI0 SDI1 SDI2 SDI3 SDI4 SDI5 SDI6 SDI7 SDOMCK SDOBCK SDOWCK SDO0 SDO1 SDO2 SDO3 SDO4 SDO5 SDO6 SDO7 /INT /MUTE GPIO0 GPIO1 GPIO2 GPIO3 /RST XI I/O Note 1) Is Is I Ot Is Is I I Function SPI chip select input SPI clock input SPI address/data input SPI data output Connect this pin to a pull-up resistor. Master clock input Bit clock input for serial data input Word clock input for serial data input Serial data input Connect unused pins to a ground.
Serial data interface
Ot Is/O I/O O
Master clock output Bit clock I/O for serial data output Input during slave mode and output during master mode. Word clock I/O for serial data output Input during slave mode and output during master mode. Serial data output Connect unused pins to a ground.
O O I+/O
Is I
8
XO
O
Test
5 6 14 15 60
TEST0 TEST1 TEST2 TEST3 TEST4
Is
Interrupt report output Auto mute report output General-purpose I/O ports Register settings are used to switch between input and output mode. Pull-up during input, no pull-up during output. Connect unused pins to a ground. Hardware reset input This LSI is initialized when at low level. Clock input Connect this pin to a 12.288 MHz crystal oscillator, such as in the part of the circuit example indicated by Note 2. If a crystal oscillator has not been connected, input a 12.288 MHz clock to the XI pin. Clock output Connect as shown by Note 2 in the circuit example. If inputting a clock directly to the XI pin (without connecting a crystal oscillator), do not connect anything to the XO pin. Do not use the XO pin for any purpose other than clock oscillation. Test input Connect to a ground.
7
YSS950
Type Power supply Pin No. 26 39 55 9 24 25 40 41 56 57 62 64 3 4 16 17 32 33 48 49 61 1 63 2 Pin Name VDD33 I/O Function Note 1) Digital power supply for pin block (Typ. 3.3 V) -
VDD12
-
Digital power supply for Core block (Typ. 1.2 V)
PAVDD PDVDD VSS
- - -
Power supply for PLL analog block (Typ. 1.2 V) Insert a 0.1 F capacitor between the PAVDD and PAVSS pins. Power supply for PLL digital block (Typ. 1.2 V) Insert a 0.1 F capacitor between the PDVDD and PDVSS pins. Digital ground
PAVSS PDVSS
- -
PLL analog ground Insert a 0.1 F capacitor between the PAVDD and PAVSS pins. PLL digital ground Insert a 0.1 F capacitor between the PDVDD and PDVSS pins.
Note 1)
* * * * *
I/O symbols
* Built in pull-up circuit cannot be used for Hi-level output of the LSI, because of this ability is only keep Hi-level for input pin when it is open.
Note 2) Example of circuit connected to crystal oscillator
XI XO
12.288 MHz
* The above resistor and capacitor values vary depending on a crystal oscillator. Be sure to meet the specifications for the crystal oscillator to be used.
8
YSS950
Register list
Default Address Byte Name Access Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F ChipAdr OpMod PLL0 PLL1 GPIODir GPOSel GPI GPO DSPCtl OMA0 OMA1 OMA2 RTCtl0 RTCtl1 SDIClk SDIFmt0 SDIFmt1 SDIFmt2 SDIMute0 SDIMute1 SDISel0 SDISel1 SDISel2 SDISel3 SDISel4 SDISel5 SDISel6 SDISel7 SDOClk0 SDOClk1 SDOFmt0 SDOFmt1 SDOFmt2 R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00 0x00 0x36 0x84 0x00 0x00
Undefine d
Bit 7 CAE SWRSTN
Bit 6 0 PD
Bit 5 0 0
Bit 4 0 0
Bit 3
Bit 2 CA[3:0]
Bit 1
Bit 0
HWRST[3:0] PLLF[7:0]
PLLOD[1:0] 0 0 0 0 BYPASS OMA 0 0 0 0 DSPMOD 0
0 0 0 0 0 0 0 OMAA[15:8] OMAA[7:0] 0 0 0 0 RAMCNFG 0
PLLR[4:0] GPIOD[3:0] GPOSEL[3:0] GPI[3:0] GPO[3:0] 0 OMAA[20:16] ICHCNFG[1:0]
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x10 0x32 0x54 0x76 0x98 0xBA 0xDC 0xFE 0x00
RTREQ 0 0
0 0 0
0
0
0 RTCNT[5:0]
0
0
0
SDIWCKS[1:0] SDITFMT[1:0] SDI2DFMT[1:0] SDI6DFMT[1:0] SDI2RMTN SDI6RMTN SDI2LMTN SDI6LMTN SDIBIT[1:0]
SDIBCKS[3:0] SDIWCKP SDIBCKP
SDITMOD[1:0] SDI3DFMT[1:0] SDI7DFMT[1:0] SDI3RMTN SDI7RMTN SDI3LMTN SDI7LMTN
SDI1DFMT[1:0] SDI5DFMT[1:0] SDI1RMTN SDI5RMTN SDI1LMTN SDI5LMTN
SDI0DFMT[1:0] SDI4DFMT[1:0] SDI0RMTN SDI4RMTN SDI0LMTN SDI4LMTN
SDI01SEL[3:0] SDI03SEL[3:0] SDI05SEL[3:0] SDI07SEL[3:0] SDI09SEL[3:0] SDI11SEL[3:0] SDI13SEL[3:0] SDI15SEL[3:0] SDOMCKD 0 0 0 0 0
SDI00SEL[3:0] SDI02SEL[3:0] SDI04SEL[3:0] SDI06SEL[3:0] SDI08SEL[3:0] SDI10SEL[3:0] SDI12SEL[3:0] SDI14SEL[3:0] SDOMCKS[2:0] SDOBCKS[3:0] SDOBIT[1:0] SDO1DFMT[1:0] SDO5DFMT[1:0] SDOWCKP SDOBCKP
0x00 SDOBWCKD 0x00 0x00 0x00 0x00 0x00 0x10 0x32 0x54 0x76 0x98 0xBA 0xDC 0xFE 0x00 0x00 0x00 0x00 0x00 IMSERR IRSERR MUTEN
SDOWCKS[1:0] SDOTFMT[1:0] SDO2DFMT[1:0] SDO6DFMT[1:0]
SDOTMOD[1:0] SDO3DFMT[1:0] SDO7DFMT[1:0]
SDO0DFMT[1:0] SDO4DFMT[1:0]
SDOMute0 R/W SDOMute1 R/W SDOSel0 SDOSel1 SDOSel2 SDOSel3 SDOSel4 SDOSel5 SDOSel6 SDOSel7 IMsk IReq Mute SDIFs SDOFs R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R
SDO3RMTN SDO3LMTN SDO2RMTN SDO2LMTN SDO1RMTN SDO1LMTN SDO0RMTN SDO0LMTN SDO7RMTN SDO7LMTN SDO6RMTN SDO6LMTN SDO5RMTN SDO5LMTN SDO4RMTN SDO4LMTN SDO0RSEL[3:0] SDO1RSEL[3:0] SDO2RSEL[3:0] SDO3RSEL[3:0] SDO4RSEL[3:0] SDO5RSEL[3:0] SDO6RSEL[3:0] SDO7RSEL[3:0] 0 0 0 IMMTBEG IRMTBEG 0 IMMTEND IRMTEND 0 SDIFS[7:0] SDOFS[7:0] 0 0 SDO0LSEL[3:0] SDO1LSEL[3:0] SDO2LSEL[3:0] SDO3LSEL[3:0] SDO4LSEL[3:0] SDO5LSEL[3:0] SDO6LSEL[3:0] SDO7LSEL[3:0] IMFW[3:0] IRFW[3:0] SDOMTSET SDIMTSET
9
YSS950
Default Address Byte Name Access Value 0x30 : FWCtl R/W 0x00 0x38 0x39 0x3A : 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F OMASum FWCtl Reserved Reserved Reserved Rserved DevID0 DevID1 R/W R/W R R R R R R 0x00 0x00 0x00 0x00 0x00 0x00 0x09 0x50 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
This is used for firmware control. For details, see the firmware manual.
OMASUM[7:0]
This is used for firmware control. For details, see the firmware manual.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVID[15:8] DEVID[7:0] 0 0 0 0 0 0 0 0 0 0 0 0
[Note] Indicates area that is accessible during the normal operation mode, the software reset mode, and the power-down mode. Indicates area that is accessible during the normal operation mode and the software reset mode. Reserved area. When writing, write only "0" to this area. Undefined when read.
0
10
YSS950
FUNCTION DESCRIPTION
1 Serial Peripheral Interface
This LSI provides a four-wire serial peripheral interface (SPI) for the /CS, SK, SI, and SO pins. The microcontroller accesses the following via this serial peripheral interface * Register address * On-chip memory access (firmware download) The following is a status transition diagram for the serial peripheral interface.
/CS=L Register settings for on-chip memory access
Device not selected
/CS=H
Register access
On-chip memory access
(Firmware download)
/CS=H
[Note] In this manual, "register access" is the means of accessing on-chip memory, and should be considered as functionally similar to "firmware download".
(a) Register access
Register access is performed in 16-bit units via the serial peripheral interface. SI is used to specify the register address (7 bits: A6 to A0) and the read/write setting (1 bit: R/W). During a write operation (R/W = L), data (8 bits: D7 to D0) should be written to SI, and during a read operation (R/W = H), 8-bit data should be read from SO. The write data is stored internally at the rising edge of SCK in the last data bit (D7 in the diagram). The serial peripheral interface sequence during register access is illustrated below.
/CS SCK
Don't care Don't care
SI SO
Don't care High-Z
A0
A1
A2
A3
A4
A5
A6 R/W D0
D1
D2
D3
D4
D5
D6
D7 Don't care
Write operation (R/W = L)
SI SO
Don't care High-Z
A0
A1
A2
A3
A4
A5
A6 R/W
Don't care High-Z
D0
D1
D2
D3
D4
D5
D6
D7
Read operation (R/W = H)
[Note] * SO is in output mode only during data read operations when /CS = L. Otherwise, high impedance output is set, so that SCK, SI, and SO can be shared with other devices that have a similar interface. * Continuous register access is enabled when /CS = L. There is no need to set /CS = H between access times. * During a hardware reset (/RST = L), keep /CS to high level (/CS = H).. * If /CS = H is set during register access, access is stopped. Any write operation that occurs prior to the rising edge of the 16th SCK signal (SI's D7 data capture clock) is invalid. SO is set to high impedance.
11
YSS950
(b) On-chip memory access
Access to on-chip memory is performed in 32-bit units via the serial peripheral interface. Also, on-chip memory access can be performed with register access. The following describes the two operation modes that are provided for this LSI.
1) Burst transfer mode
Burst transfer mode can be used to download instruction code/coefficient data firmware. By using this mode, a large amount of data can be downloaded at high speeds when initialization is executed or when the sampling frequency is changed. The features of the burst transfer mode are as follows. * * * * Stops signal processing during high-speed transfers Muting is automatically effected during transfer period. Transfers from microcontrollers can be accepted immediately, without handshaking Both instruction code firmware and coefficient data firmware can be downloaded.
The burst transfer steps for on-chip memory access are illustrated below.
(1) (2) (3) (4)
/CS SCK
A D0 A D1 A D2 A D3 A A A A A+1 A+1 A+1 A+1 D28 D29 D30 D31 D0 D1 D2 D3 Don't care
SI SO (OMA) (OMAA)
D4 High-Z
D5
D6
D7
A+n A+n A+n A+n Don't care D28 D29 D30 D31
A
A+1
A+n
A+n +1
<1> Setup: * Initialize the checksum as necessary. OMASUM[7:0]=0 * Set the on-chip memory access start address (example: OMAA[20:0] = A). * Change the serial peripheral interface pin function from register access to on-chip memory access (OMA = 1). <2> Start: * Data is transferred LSB first, in 32-bit units. * Data is captured at the rising edge of SCK in the 32nd data bit (D31). <3> Continuation: * Next, transfer data at consecutive address in 32-bit units. * The on-chip memory address (OMAA[20:0]) is automatically incremented each time 32 bits of data are written. <4> Completion and post-completion processing: * On-chip memory access ends (OMA = 0) automatically when /CS = H is set. * OMAA[20:0] is notified of the start address and transfer data number. (E.G. OMAA[20:0]= A+n+1) * OMASUM[7:0] is notified of the checksum of the transferred data. [Note] * Burst transfer can be interrupted by setting /CS to high level. If burst transfer is interrupted before the rising edge of SCK in the 32nd data bit, the write operation is not performed. * When transferring to non-consecutive addresses or when re-executing after a transfer has been interrupted, start from step (1) above. * When data is at consecutive addresses, the data at the transfer start address should be transferred with the start bit incremented each time according to the address order.
12
YSS950
2) Runtime transfer mode
During runtime transfer mode, coefficient data firmware can be downloaded. This mode enables the coefficient to be changed without jitter, even during signal processing. The runtime processing mode's features are listed below. * Transfers are performed while signal processing is continued. Auto mute is not set during the transfer period. * Up to 32 words of transfer data is buffered and written to on-chip memory as a batch. * Downloading of coefficient data firmware is supported. The runtime transfer mode's steps for on-chip memory access are illustrated below.
(1)
/CS
16 SCKs 16 SCKs 16x3 SCKs 32 SCKs 32x(n-1) SCKs Don't care Write RTCNT=0 Write OMASUM=0 Write OMAA=A,OMA=1 0 Write D[0] Write D[1] 1 Write D[n-1] n-1
SCK SI (RTCNT) (OMA)
Don't care
n
<1> Setup (transfer to on-chip buffer) * Initialize the transfer data count (RTCNT[5:0] = 0). * Initialize the checksum as necessary. OMASUM[7:0]=0 * Set the start address for on-chip memory (example: 0MAA[20:0] = A). * Change the serial peripheral interface's pin function from register access to on-chip memory access (OMA = 1). * The specified amount of data at consecutive addresses is transferred in 32-bit units, and in LSB first sequence. * The transfer data count (RTCNT[5:0]) is automatically incremented each time 32 bits of data are written. * Transfer of data to on-chip buffers ends when /CS = H is set.
(2) (3)
/CS
16 SCKs 16 SCKs 16 SCKs Don't care Write RTREQ=1 Read RTREQ Read RTREQ
SCK SI SO (RTCNT) (OMAA) (RTREQ)
Don't care
Don't care High-Z
Don't care
n
A
<2> Start (transfer from on-chip buffer to on-chip memory) * Start of data transfer is requested (RTREQ = 1). <3> End * End of data transfer is confirmed (RTREQ = 0, IRFW[0]=1). * OMASUM[7:0] is notified of the checksum of the transferred data. [Note] * On-chip buffer transfer can be interrupted by setting /CS to high level. If a transfer is interrupted before the rising edge of SCK in the 32nd data bit, the write operation is not performed. * When transferring to non-consecutive addresses or when re-executing after the on-chip buffer transfer has been interrupted, start from step (1) above.
13
YSS950
* When data is at non-consecutive addresses, the data at the transfer start address should be transferred with the start bit incremented each time according to the address order. * Up to 32 words of data can be transferred as data at consecutive addresses. When transferring more than 32 words of data to consecutive addresses, stop after each 32 words and resume from step (1) above. * OMAA[20:0] is not automatically incremented.
14
YSS950
2 Serial Data Interface
[Note] The following serial data interface control register (addresses 0x0E to 0x2A, except SD*MTN) and ICHCNFG[1:0] (address 0x08) should be set in the software reset mode. If changes are required when in the normal operation mode, perform the following steps to prevent abnormal sounds. <1> Set mute (SD*MTN = 10, SD*MTSET = 1). <2> Set the DSP mode to on-chip memory access burst transfer mode (DSPMOD = 10). <3> Set serial data interface control register /ICHCNFG[1:0]. <4> Wait for at least 1024 samples. <5> Set the DSP mode to signal processing mode (DSPMOD = 01). <6> Cancel mute (SD*MTN = 01, SD*MTSET = 1).
(a) Interface clock control
Registers
SDIWCKS[1:0] SDOWCKS[1:0] SDIBCKS[3:0] SDOBCKS[3:0] SDOMCKS[2:0] SDOWBCKD SDOMCKD
SDIMCK
1/2 1/4 1/6 1/8 1/12
0 1 2 3 4 5
SDOMCK
sel
4 5 6 7 8
4 5 6 7 8 9
SDIBCK
9 0
sel
1/2 1/4 1/8
0 1 2 3
SDOBCK
sel
1/64 1/128 1/256
1 2 3 0
1/64 1/128 1/256
1 2 3 0
SDIWCK
sel
sel
1 0 1 0
SDOWCK
sel sdibck Serial Data Input sdiwck sdobck
sel sdowck
Serial Data Output
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YSS950
(b) Interface format
1) Input format
The normal mode timing is illustrated below. 32-bit data can be input via the two channels from SDI0, SDI1, SDI2, SDI3, SDI4, SDI5, SDI6, and SDI7. (n) indicates the current frame input sample and (n - 1) indicates the previous frame input sample.
1 frame (1/fs = 64 SDIBCKs)
SDIWCK
SDIWCKP=0
SDIWCKP=1 32 SDIBCKs 32 SDIBCKs
SDIBCK
SDIBCKP=0
SDIBCKP=1 SDI*L(n) SDI*R(n)
L S B 1 0 M S B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 14 12 1 L S B 0
SDI*
SDITFMT=0b00 SDIBIT=0bxx
M S B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
SDI*L(n) SDITFMT=0b10 SDIBIT=0bxx
M S B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 2 1 L S B 0
SDI*R(n)
L S B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 2 1 0
SDI*R(n-1) SDITFMT=0b01 SDIBIT=0b00
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L S B 0 M S B 31 30 29 28
SDI*L(n)
L S B 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M S B
SDI*R(n)
31 30 29 28
17 16
SDI*R(n-1) SDITFMT=0b01 SDIBIT=0b01
13 12 11 10 9 8 7 6 5 4 3 2 1 L S B 0 M S B 31 30 29 28 27 26
SDI*L(n)
L S B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M S B
SDI*R(n)
31 30 29 28 27 26
15 14
SDI*R(n-1) SDITFMT=0b01 SDIBIT=0b10
11 10 9 8 7 6 5 4 3 2 1 LM SS BB 0 31 30 29 28 27 26 25 24
SDI*L(n)
L S B 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M S B
SDI*R(n)
31 30 29 28 27 26 25 24
13 12
SDI*R(n-1) SDITFMT=0b01 SDIBIT=0b11
7 6 5 4 3 2 1 L S B 0 M S B
SDI*L(n)
L S B 9 8 7 6 5 4 3 2 1 0 M S B
SDI*R(n)
31 30 29 28 27 26 25 24 23 22 21 20
31 30 29 28 27 26 25 24 23 22 21 20
9
8
16
YSS950
The TDM 4ch mode timing is illustrated below. 32-bit data can be input via the four channels from SDI0, SDI2, SDI4, and SDI6. The supported data format is the same as for normal mode.
1 frame (1/fs = 128 SDIBCKs)
SDIWCK
SDIWCKP = 0
SDIWCKP = 1 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs
SDIBCK
SDIBCKP = 0
SDIBCKP = 1
SDI0 SDI2 SDI4 SDI6
SDI0L(n)
SDI0R(n)
SDI1L(n)
SDI1R(n)
SDI2L(n)
SDI2R(n)
SDI3L(n)
SDI3R(n)
SDI4L(n)
SDI4R(n)
SDI5L(n)
SDI5R(n)
SDI6L(n)
SDI6R(n)
SDI7L(n)
SDI7R(n)
The TDM 8ch mode timing is illustrated below. 32-bit data can be input via the eight channels from SDI0 and SDI4. The supported data format is the same as for normal mode.
1 frame (1/fs = 256 SDIBCKs)
SDIWCK
SDIWCKP = 0
SDIWCKP = 1 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs
SDIBCK
SDIBCKP = 0
SDIBCKP = 1
SDI0 SDI4
SDI0L(n)
SDI0R(n)
SDI1L(n)
SDI1R(n)
SDI2L(n)
SDI2R(n)
SDI3L(n)
SDI3R(n)
SDI4L(n)
SDI4R(n)
SDI5L(n)
SDI5R(n)
SDI6L(n)
SDI6R(n)
SDI7L(n)
SDI7R(n)
17
YSS950
2) Output format
The normal mode timing is illustrated below. 32-bit data can be output via the two channels from SDO0, SDO1, SDO2, SDO3, SDO4, SDO5, SDO6, and SDO7. (n) indicates the current frame input sample and (n - 1) indicates the previous frame output sample.
1 frame (1/fs = 64 SDOBCKs)
SDOWCK
SDOWCKP=0
SDOWCKP=1 32 SDOBCKs 32 SDOBCKs
SDOBCK
SDOBCKP=0
SDOBCKP=1 SDO*L(n) SDO*R(n)
L S B 1 0 M S B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 14 12 1 L S B 0
SDO*
SDOTFMT=0b00 SDOBIT=0bxx
M S B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
SDO*L(n) SDOTFMT=0b10 SDOBIT=0bxx
M S B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 2 1 L S B 0
SDO*R(n)
L S B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 2 1 0
SDO*R(n-1) SDOTFMT=0b01 SDOBIT=0b00
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L S B 0 M S B 31 30 29 28
SDO*L(n)
L S B 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M S B
SDO*R(n)
31 30 29 28
17 16
SDO*R(n-1) SDOTFMT=0b01 SDOBIT=0b01
13 12 11 10 9 8 7 6 5 4 3 2 1 L S B 0 M S B 31 30 29 28 27 26
SDO*L(n)
L S B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M S B
SDO*R(n)
31 30 29 28 27 26
15 14
SDO*R(n-1) SDOTFMT=0b01 SDOBIT=0b10
11 10 9 8 7 6 5 4 3 2 1 LM SS BB 0 31 30 29 28 27 26 25 24
SDO*L(n)
L S B 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M S B
SDO*R(n)
31 30 29 28 27 26 25 24
13 12
SDO*R(n-1) SDOTFMT=0b01 SDOBIT=0b11
7 6 5 4 3 2 1 L S B 0 M S B
SDO*L(n)
L S B 9 8 7 6 5 4 3 2 1 0 M S B
SDO*R(n)
31 30 29 28 27 26 25 24 23 22 21 20
31 30 29 28 27 26 25 24 23 22 21 20
9
8
18
YSS950
The TDM 4ch mode timing is illustrated below. 32-bit data can be output via the four channels from SDO0, SDO2, SDO4, and SDO6. The supported data format is the same as for normal mode.
1 fSDORame (1/fs = 128 SDOBCKs)
SDOWCK
SDOWCKP=0
SDOWCKP=1 32 SDOBCKs 32 SDOBCKs 32 SDOBCKs 32 SDOBCKs
SDOBCK
SDOBCKP=0
SDOBCKP=1
SDO0 SDO2 SDO4 SDO6
SDO0L(n)
SDO0R(n)
SDO1L(n)
SDO1R(n)
SDO2L(n)
SDO2R(n)
SDO3L(n)
SDO3R(n)
SDO4L(n)
SDO4R(n)
SDO5L(n)
SDO5R(n)
SDO6L(n)
SDO6R(n)
SDO7L(n)
SDO7R(n)
The TDM 8ch mode timing is illustrated below. 32-bit data can be output via the eight channels from SDO0 and SDO4. The supported data format is the same as for normal mode.
1 frame (1/fs = 256 SDOBCKs)
SDOWCK
SDOWCKP=0
SDOWCKP=1 32 SDOBCKs 32 SDOBCKs 32 SDOBCKs 32 SDOBCKs 32 SDOBCKs 32 SDOBCKs 32 SDOBCKs 32 SDOBCKs
SDOBCK
SDOBCKP=0
SDOBCKP=1
SDO0 SDO4
SDO0L(n)
SDO0R(n)
SDO1L(n)
SDO1R(n)
SDO2L(n)
SDO2R(n)
SDO3L(n)
SDO3R(n)
SDO4L(n)
SDO4R(n)
SDO5L(n)
SDO5R(n)
SDO6L(n)
SDO6R(n)
SDO7L(n)
SDO7R(n)
19
YSS950
3 Status
These informations are notified from LSI. < > Interrupt report < > Auto mute report < > Sampling frequency report
4
General-Purpose I/O Ports
General-purpose I/O ports GPIO3 to GPIO0 implement the following functions. I/O polarity switching is performed by GPIOD[3:0]. <1> Input port: Pin status is read via GPI[3:0]. <2> Output port: GPO[3:0] or DSP status is output to a pin. Switching of output contents is performed by GPOSEL[3:0]. <3> Chip address port: The port is used as chip address input for selection of a chip to share (CAE=1)..
GPOSEL[x] (register)
GPIOD[x] (register)
GPI[x] (register) CA comparison GPO[x] (register) DSP Status[x]
Pull-up circuit
GPIOx (pin)
sel
20
YSS950
ELECTRICAL CHARACTERISTICS
1 Absolute Maximum Ratings
Min. -0.5 -0.5 -0.5 -0.5 -50 Typ. Max. 4.6 1.68 5.5 4.6 125 Unit V V V V C Symbol Conditions [Note 1] VDD33 VDD12 [Note 1] Power supply voltage 2 (1.2 V) PAVDD [Note 1] PDVDD [Note 1] [Notes 1 and 2] Input voltage 1 VI1 [Notes 1 and 3] Input voltage 2 VI2 Storage temperature TSTG [Note 1] All GND pins (VSS, PAVSS, and PDVSS) are 0 V. [Note 2] Applies to all input pins other than XI (5 V tolerant). [Note 3] Applies to the XI pin. Parameter Power supply voltage 1 (3.3 V)
2
Recommend Operating Conditions
Min. 3.0 1.1 -40 Typ. 3.3 1.2 25 Max. 3.6 1.3 85 Unit V V C
Symbol Conditions [Note 1] VDD33 [Note 1] VDD12 Power supply voltage 2 (1.2 V) [Note 1] PAVDD [Note 1] PDVDD Operating temperature TOP [Note 1] All GND pins (VSS, PAVSS, and PDVSS) are 0 V.
Parameter Power supply voltage 1 (3.3 V)
3
Current Consumption
(a) During normal operation mode
Parameter Conditions Min. Typ. Max. Unit Power consumption mW [Notes 1 and 2] 130 VDD33 current consumption mA [Notes 1 and 2] 7 VDD12 + PAVDD + PDVDD current consumption [Notes 1 and 2] mA 89 [Note 1] Typical values are typical under the recommended operation conditions. Maximum values are maximum values under the recommended operation conditions. However, the input pin's high-level voltage value is VDD33 and the low-level input voltage value is VSS. [Note 2] This depends on the sampling frequency and firmware. The firmware used in this case requires a processing load of approximately 150 MHz at a sampling frequency of 48 kHz.
(b) During power-down mode
Parameter Conditions Min. Typ. Max. Unit Power consumption mW [Notes 1] 1 VDD33 current consumption [Notes 1] A 6 VDD12 + PAVDD + PDVDD current consumption mA [Notes 1] 1 [Note 1] Typical values are typical under the recommended operation conditions. Maximum values are maximum values under the recommended operation conditions. However, the input pin's high-level voltage value is VDD33 and the low-level input voltage value is VSS. [Note 2] The current consumption increases at higher temperatures.
21
YSS950
4 DC Characteristics
Parameter Symbol Conditions Min. Typ. Max. Unit V V V V V V
5.25 High level input voltage 1 VIH1 2.0 [Note 1] 0.8 Low level input voltage 1 VIL1 [Note 1] VDD33 High level input voltage 2 VIH2 [Note 2] 0.8VDD33 Low level input voltage 2 VIL2 [Note 2] 0.2VDD33 High level output voltage VOH [Note 3] 2.4 Low level output voltage VOL [Note 4] 0.4 Input leakage current 1 [Note 5] II1 10 Input leakage current 2 [Note 6] II2 +10/-125 Capacitance of input pin CI 5 [Note 1] Applies to all input pins other than XI (5 V tolerant). [Note 2] Applies to XI pin. [Note 3] (Output level is not rated.) Applies to all input pins other than XO. However, IOH = -1.0 mA. [Note 4] (Output level is not rated.) Applies to all output pins other than XO. However, IOL = 1.0 mA. [Note 5] Applies to all input pins other than GPIO. [Note 6] Applies to GPIO pin.
A A
pF
22
YSS950
5 AC Characteristics
(a) System
Parameter Power-on and power-off time XI clock frequency XI clock duty factor Internal clock frequency /RST time 1 Symbol tV3V1 fXI dXI fCLK tRST1 Conditions [Note 1] Min. -1 12.288 40 165.888 60 Typ. Max. 1 Unit s MHz % MHz ms
5 At power-on During /RST time 2 tRST2 1 normal s operation [Note 1] The power on/off interval between systems with 3.3 V power supplies and systems with 1.2 V power supplies should be within one second. The LSI can be damaged if either type of power supply is left on while turning on the other.
1) At power-on
VDD33
tV3V1 tRST1
VDD12, PAVDD, PDVDD XI
/RST
* If a crystal oscillator is connected, this includes the time between power supply stabilization and oscillation stabilization. * Turn on the power when /RST = L.
2) During normal operation
tRST2
/RST
* This condition is that both XI input and the power supply must be stabilized. * If XI oscillation stops while initializing in the power-down mode, some time is needed to stabilize oscillation again.
23
YSS950
(b) Serial peripheral interface
Conditions Parameter Symbol Min. Typ. SCK cycle tSCK 80 SCK high level time tSCKH 40 SCK low level time tSCKL 40 /CS high level time tCSH 80 /CS and SI setup time tSIS 10 [Note 1] /CS and SI hold time tSIH 10 [Note 1] SO delay time tSOD CL = 50 pF SO disable time tSOZ CL = 50 pF [Note 1] Satisfy the setup time/hold time (vs. SCK) on starting or ending transfer, with /CS = L. Max. Unit ns ns ns ns ns ns ns ns
30 20
/CS
tSIS tSCK tSCKL tSIH
tCSH
SCK
tSIS
tSCKH tSIH
SI
tSOD
High-Z
tSOZ
SO
24
YSS950
(c) Serial data interface
1) SDIMCK
SDIMCK input frequency SDIMCK duty factor
fSDIMCK dSDIMCK
SDIMCK
dSDIMCK
2) SDOMCK
Conditions Parameter Symbol Min. Typ. Max. Unit SDOMCK output frequency fSDOMCK 40 MHz SDOMCK duty factor dSDOMCK 50 % [Note 1] SDOMCK rise time tSDOMCKR CL = 50 pF 10 ns SDOMCK fall time tSDOMCKF CL = 50 pF 10 ns [Note 1] When SDOMCKS[2:0] = 0b00 has been set and "through" has been selected for SDIMCK, it is affected by the SDIMCK duty factor.
fSDOMCK dSDOMCK
SDOMCK
tSDOMCKR tSDOMCKF
dSDOMCK
25
YSS950
3) SDIBCK, SDIWCK, SDI7 to SDI0 (slave mode)
Conditions Parameter Symbol Min. Typ. Max. SDIBCK input frequency fSDIBCK 12.5 SDIBCK duty factor dSDIBCK 50 [Note 1] SDIWCK, SDI7 to SDI0 setup time tSDIS 10 SDIWCK, SDI7 to SDI0 hold time tSDIH 15 [Note 1] The polarity of SDIBCK can be changed by SDIBCKP. In the following figure, SDIBCKP = 0.
fSDIBCK dSDIBCK
Unit MHz % ns ns
SDIBCK
tSDIS tSDIH
dSDIBCK
SDIWCK
tSDIS tSDIH
SDI7-0
4) SDOBCK, SDOWCK, SDO7 to SDO0 (slave mode)
Conditions Parameter Symbol Min. Typ. Max. SDOBCK input frequency 12.5 fSDOBCK SDOBCK duty factor 50 dSDOBCK [Note 1] SDOWCK setup time 10 tSDOWCKS SDOWCK hold time 10 tSDOWCKH SDO7 to SDO0 delay time CL = 50pF 30 tSDOD [Note 1] The polarity of SDOBCK can be changed by SDOBCKP. In the following figure, SDOBCKP = 0.
fSDOBCK dSDOBCK
Unit MHz % ns ns ns
SDOBCK
tSDOWCKS tSDOWCKH
dSDOBCK
SDOWCK
tSDOD
SDO7 to SDO0
26
YSS950
5) SDOBCK, SDOWCK, SDO7 to SDO0 (master operation)
Conditions Min. Typ. Max. Unit 12.5 MHz [Note 2] 50 % [Note 1, 3] CL = 50 pF 15 ns CL = 50 pF 15 ns CL = 50 pF 15 ns -15 CL = 50 pF ns 0 tSDOBCKD SDIBCK SDOBCK delay time [Note 4] [Note 1] The polarity of SDIBCK and SDOBCK can be changed by SDIBCKP and SDOBCKP. In the following figure, SDIBCKP = SDOBCKP = 0. [Note 2] Although output divided from SDIMCK can be selected for SDOBCK via SDOBCKS[2:0], operation is not guaranteed if SDIMCK's frequency exceeds the range noted above. [Note 3] When SDIBCKS through has been selected by SDIBCKS[3:0] = SDOBCKS[3:0] = 0b0000, output is affected by the SDIBCK duty factor. [Note 4] When SDIBCKS through has been selected by SDIBCKS[3:0] = SDOBCKS[3:0] = 0b0000. Parameter SDOBCK output frequency SDOBCK duty factor SDOBCK rise time SDOBCK fall time SDOWCK, SDO7 to SDO0 delay time Symbol fSDOBCK dSDOBCK tSDOBCKR tSDOBCKF tSDOD
tSDOBCKD
SDIBCK
fSDOBCK dSDOBCK
tSDOBCKR
tSDOBCKF
SDOBCK
tSDOD
dSDOBCK
SDOWCK
tSDOD
SDO7 to SDO0
27
YSS950
PACKAGE DIMENSIONS
28
YSS950

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